IEEE Instrumentation and Measurement Technology Conference Budapest Hungary May A Noise Shaping Accelerometer Interface Circuit for Two Chip Implementation
نویسنده
چکیده
A proposed third order noise shaping accelerometer interface circuit enhances the SNR compared with the previ ously presented interface circuits The solution for the two chip implementation is described and a novel cross coupled CDS integrator is proposed This scheme functions even with the large parasitic capacitances between the sensor and the interface circuit The op amp noise is rst order shaped Dithering circuit is also implemented on the chip fabricated in AMI m CMOS process
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A two-chip interface for a MEMS accelerometer
A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is proposed. This scheme functions even with large parasitic capacitances between the sensor and the interface circ...
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1 ENZ, c.c., and TEMES, G.C : 'Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization', Proc. IEEE, 1996, 84, pp. 1584-1614 2 KAJITA, T. , MOON, U,-K., and TEMES, G.C.: 'A noise-shaping accelerometer interface circuit for two-chip implementation'. IEEE ISCAS 2000, May 2000, pp. IV-337-IV-340 3 STEENSGAARD, I.: 'Clo...
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